As is known, a generic electronic integrated circuit is provided in a die (or, as used hereinafter, a chip) of semiconductor material, which is obtained, at the end of the manufacturing process, by dicing a wafer. The wafer generally comprises an active layer (for example, formed by a surface portion of a substrate), integrating one or more electronic components (either active or passive, for example transistors), or parts thereof, and one or more metallization and electrical-insulation layers extending on the active layer, to obtain the electronic components and their electrical interconnections.
The electrical connection between the electronic integrated circuit within the chip and an external electronic system is in general provided by conductive contact pads carried by an outer top surface of the chip, and electrical-connection wires that extend from the conductive pads towards similar connection elements of the external electronic system (this connection technique is generally known as “wire bonding” technique). In particular, the conductive pads form the terminations of electrical lines present in the chip and are designed for conveying information signals or power signals (among which electrical-supply signals for the electronic integrated circuit).
An alternative technique of electrical connection envisages use of conductive elements, projecting contact protuberances, or conductive balls or bumps, or conductive lands, directly connected to the conductive pads of the chip and set between the conductive pads themselves and similar connection elements of the external electronic system. In this case, the connection technique is usually defined as a “flip-chip technique”, in so far as it envisages that the chip will be turned upside down in such a way that its outer top surface, which carries the conductive pads, is arranged facing the printed circuit board, or further electronic device, of the external electronic system.
In the field of electrical connections of electronic integrated circuits, moreover known is the use of the so-called through silicon vias (in what follows simply “through vias”), i.e., interconnections of conductive material that extend vertically through the chip of the electronic integrated circuit, enabling electrical connection of elements of the circuit, integrated at various levels of the structure of the chip, with an external surface thereof. The through vias are developed vertically through the chip and the corresponding substrate in such a way that, at the end of the manufacturing process, i.e., in their final form of use, they will be accessible from the outer surface of the chip designed for connection with the printed circuit board, or further electronic device, of the external electronic system, for example by being electrically contacted by the contact elements (bumps, balls, or lands) carried by said surface.
Generally, the through vias are electrically insulated from the substrate that they traverse in so far as they are insulated both laterally and underneath by an electrical-insulation region, for example constituted by dielectric material, in such a way as to avoid the presence of leakage currents towards the substrate itself.
FIG. 1 shows in a schematic and simplified way a generic electronic integrated circuit (IC) 1, provided in a wafer 2, comprising a substrate 3 of semiconductor material, integrated within which are, at least in part, electronic components 4, for example MOSFETs (as indicated schematically). In particular, the substrate 3 has a front surface 3a, in a position corresponding to which the electronic components 4 are provided, and a back surface 3b, opposite to the front surface 3a. 
Arranged on the substrate 3, on one or more levels superimposed on one another, are electrical-insulation and metallization layers, schematically represented in FIG. 1 by an insulation layer 5, arranged on the front surface 3a of the substrate 3, and at least one metallization layer 6, arranged on the insulation layer 5. In a known way, appropriate structures, either conductive or insulating, of the electronic components 4 may moreover extend on the substrate 3 (for example, to obtain a gate oxide and a gate conductive structure of a MOSFET). In addition, the insulation and metallization layers 5, 6 provide the electrical connections between the electronic components 4, and the electrical connections towards the outside of the electronic integrated circuit 1.
Moreover, a passivation layer 7, of insulating material, extends on the metallization layer 6; contact pads 8 are opened in the passivation layer 7, are electrically connected to the metallization layer 6 and are designed to be electrically contacted from the outside. The outer surface of the passivation layer, designated by 7a, is a front outer face of the wafer 2.
In particular, in the substrate 3 the electronic components 4 are provided through appropriate processes designated as a whole by FEOL (Front End of Line), whereas the remaining electrical-insulation layers 5, metallization layers 6 that provide the electrical connections towards the outside, and the passivation layer 7 are designated as a whole by BEOL (Back End of Line).
Moreover one or more through vias are formed inside the wafer 2, designated as a whole by 10, including conductive interconnections that extend vertically through the substrate 3 and possibly traverse one or more of the electrical-insulation and metallization layers 5, 6, so as to define electrical connections between the electronic components 4, the metallization layers 6, or the contact pads 8, towards the back of the substrate 3. In particular, by way of example, FIG. 1 shows a first through via 10′, which extends from the front surface 3a towards the back of the substrate 3, being designed to contact a region of an electronic component 4 (for example, a region of a MOSFET); a second through via 10″, which extends from a metallization layer 6 towards the back of the substrate 3; and a third through via 10′″, which extends from the outer surface 7a of the passivation layer 7 towards the back of the substrate 3, being designed to contact a contact pad 8.
It is noted that, after their formation, the through vias 10 are generally insulated and “embedded” within the substrate 3 of the wafer 2, being separated from the back surface 3b of the substrate 3 by a portion of material having a given thickness.
For example, the through vias 10 may be obtained as described in United States Patent Applicant Publication No. 2005/0101054, or in “Wafer Level 3-D ICs Process Technology”, of Chuan Seng Tan, Ronald J. Gutmann and L. Rafael Reif, pp. 85-95, Springer-Verlag New York Inc., which are incorporated by reference.
FIG. 2 shows the electronic integrated circuit 1 at the end of the manufacturing process: a final step of thinning the back of the substrate 3 (with known techniques of lapping, or “back grinding”) exposes a portion of the back end of the through vias 10, which may in this way be contacted electrically from outside. Following upon the thinning process, the substrate 3 has a reduced thickness, for example even of less than 50 μm.
In one of the possible assembly processes, the wafer 2 is next diced so as to define a plurality of chips, each of which contains a respective electronic integrated circuit.
At the end of the manufacturing process, the through vias 10 thus traverse the entire substrate 3, providing a direct electrical connection from the electronic components 4 to the metallization layers 6 within the chip, or to the contact pads 8 from the back surface 3b of the substrate 3 (which in this case forms an outer back face of the chip), or more in general one or more electrical connections from the so-called “top” (i.e., the front part) of the chip, to the so-called “bottom” (i.e., the back part) of the chip.
The use of the through vias 10 may particularly advantageous for providing three-dimensional packaging structures for the electronic integrated circuits (the so-called “3D-packaging techniques”), which have been recently proposed in the field of semiconductors in general and of microelectromechanical systems (MEMS) in particular.
It is noted that, in a way that is usual in this sector of the art, the term “package” is here used for designating, as a whole, the casing, or covering structure, which surrounds, totally or partially, the chip or chips of semiconductor material of the electronic integrated circuit, enabling electrical connection thereof with the outside (for example, connection to a printed circuit of a corresponding external electronic system).
In a known way, 3D-packaging techniques envisage alternatively: vertical stacking of two or more packages, each enclosing one or more electronic integrated circuits (the so-called “package-level 3D packaging”); vertical stacking of two or more chips or dice (the so-called “chip-level 3D packaging”); and vertical stacking of two or more wafers (the so-called “wafer-level 3D packaging”). In particular, in the latter case, the wafers are stacked on one another and then diced before they are enclosed within a corresponding package. Clearly, to be able to provide the electrical connections between the electronic integrated circuits in the various wafers appropriately arranged through vias may be required.
The use of three-dimensional structures enables an increase in the density of the interconnections, at the same time reducing the length thereof, thus reducing also the parasitic effects; it may thus be possible to increase their performances. The use of through vias may thus be advantageous in a wide range of applications, in particular for reducing the length of the connections between the various chips, dice, or wafers.
The above use entails, however, various problems of production, linked, for example, to the etching processes required for forming vias/trenches having a small diameter (even of less than approximately 10 μm) and a large depth within the chip, or to the alignment processes between the wafers, chips, or dice. Also in the light of the critical aspects of the production process, and given the nature of electrical interconnection performed by the through vias, it would be advantageous to be able to verify proper operation thereof (for example before manufacturing the integrated circuits and in particular before completing dicing of the wafer of semiconductor material), and in particular to verify the resistance of the path offered to the electric current circulating through the through vias and moreover verify the presence of possible leakages and parasitic phenomena, for example, in regard to the substrate.
In this regard, so-called “automatic test equipment” (ATE) are known, which perform an automatic procedure of testing and electrical sorting the various chips within a wafer of semiconductor material (before the corresponding dicing) so as to select the chips operating properly for their subsequent packaging. This operation is known as “electrical wafer sort” (EWS) or “wafer sort” (WS) and envisages execution of appropriate electrical tests on the electronic integrated circuits in the various chips.
As shown schematically in FIG. 3, a testing apparatus, designated as a whole by 15, designed to test the electrical characteristics of a wafer, once again designated by the reference number 2, as in FIGS. 1 and 2, comprises a chuck 16 (incorporated in an electromechanical apparatus referred to as “prober”, not illustrated herein), on which the wafer 2 to be tested is arranged, and a probe head 17, which is provided with a plurality of probes 18 (in a high number, ranging from several hundreds to several thousands) and can be actuated so as to approach the front face 7a of the wafer 2, thereby the probes 18 electrically contact the contact pads (not illustrated herein) of the wafer 2 in an appropriate way. To this end, the probe head 17 is coupled to a printed-circuit board 19, containing appropriate electronic circuits interconnected to an ATE (not illustrated herein), and to an electromechanical actuation system (not illustrated herein either). In use, the probe head 17, via the probes 18, may be electrically coupled with the electronic integrated circuits contained in the wafer 2 so as to measure one or more electrical parameters thereof. The ensemble of the probe head 17, of the probes 18, and of the printed-circuit board 19 constitutes a so-called “probe card”.
The testing apparatus 15 may, however, be inadequate for testing the through vias 10 at the level of the wafer of semiconductor material. In fact, the through vias 10 have terminations that are electrically insulated from, and embedded within, the substrate 3, being thus inaccessible for the probe head 17 and the corresponding probes 18. An altogether similar consideration applies to testing of through vias 10 in a stacked structure of a three-dimensional type.
In addition, the use of the probes may prove incompatible for testing through vias (also when the test is carried out after thinning the substrate, i.e., with a back portion of the through vias accessible from the back of the substrate itself). In fact, the tendency is known to progressively reduce the dimensions of the through vias, which can have dimensions of even less than approximately 10 μm; this reduction of the dimensions may render it very difficult to obtain a reliable electrical contact between the tip of the probe and the through via, since the typical size of the surface of the tip of the probe is 10 μm-15 μm greater than a corresponding dimension of the through via (also on the basis of the requirements of the test current that is to flow through the contact).
The direct contact between the probes 18 and the through vias 10 may thus damage the surface of the through vias 10, with consequent problems of loss of electrical efficiency of the interconnections in the three-dimensional stacked structures. The same problem may also arise when a conductive element (for example a bump) is formed on the through vias to obtain an electrical connection between two chips in the three-dimensional structure. In fact, in any case, the reduction of the area of contact between the probe 18 and the through vias 10 (also due to the morphology of the two surfaces in contact and to the presence on these surfaces of other non-conductive materials, such as, for example, contaminating particles, etc.) may cause an increase of the electrical resistance of the contact, overheating the contact area and locally raising the temperature even by some hundreds of degrees centigrade, upon the passage of the electrical test current.
The circumstances listed hereinafter may render still more problematical the electrical contact between the probes and the through vias: certain testing equipment is provided with probes that run on the surface of the contact pads for improving the performance of the electrical contact; the probes are not always well aligned to one another and do not maintain their centering over time; moreover, there may occur imprecise alignment between the probes and the wafer, after the operations of positioning of the chuck that carries the wafer on which the test operations are to be carried out.
In addition, when the electronic integrated circuit to be tested has a high density of through vias, it may also happen that the distance between the through vias is smaller than the minimum distance possible between two probes (due to the technology of production, for example, 50 μm), thus rendering impractical or impossible the provision of a system of a traditional type for testing the through vias.
It follows that there does not exist up to now a solution that enables electrical testing of through vias, in particular in three-dimensional structures that envisage vertical stacking of two or more wafers or chips, and in particular there does not so far exist a testing technology that is scalable with the reduction of the dimensions of the through vias, i.e., such that it is possible to reduce the dimensions of the probes by the same factor with which the dimensions of the through vias are reduced.